Semi conductor process technology has been progressing along path towards ever-smaller device geometries, providing dramatic increases the amount of circuitry which can be placed on a single-chip (i.e., increased circuit density). In general, the integrated circuit technology made available to the public in the form of custom and semi-custom devices has followed this same path, providing ever-greater numbers of gates on a single chip at ever-lower costs. One particular type of semi-custom integrated circuit device is known as an ASIC (Application Specific Integrated Circuit), which typically includes standard-cell and gate-array technologies. It is now practical to provide ASICs with hundreds of thousands of gates, even in relatively low volumes.
To some extent, ASIC technology is the beneficiary of process technology advances in other areas such as memory and microprocessor technology. Trends in these areas have also been towards smaller device geometries and higher circuit density. Memory technology, particularly DRAM (Dynamic Random-Access-Memory) technology now routinely provides four to sixteen million bits of storage on a single memory chip. Microprocessor technology has advanced to the point where million-gate microprocessors are routinely available.
The trend in newer microprocessor designs has been towards increasing parallelism, both internally and externally. Internally, more operations are performed simultaneously. Externally, microprocessor bus-widths have increased from a typical 8-bit bus width in the late 1970's to bus-widths of 64 bits and more today. These wider buses, however, place heavy demands on circuitry external to the microprocessor.
The above-referenced trends have generally been accompanied by increased demand for input/output (I/O) connections to the chip. For example, as bus-widths of microprocessors have increased, the emphasis of most ASIC users has shifted from circuit density to large numbers of I/O "pins" or connections in what would seem, at first, to run contrary to the process technology trends. The extremely wide processor buses necessitate wide buffering schemes, specialized interfaces to peripheral devices and memories with bus widths different than the processor bus width, and other specialized processor support circuitry. As a result, many ASIC users choose ASIC configurations with relatively small numbers of gates (e.g., 15,000, where 100,000 gate ASICs are available) but with relatively large numbers of I/O pins (e.g., 200 or more I/O pins).
Using early ASIC designs, an ASIC user would be forced to choose an ASIC with significantly larger circuit area than was needed, because the relatively large I/O pads (bond pads) on ASIC chips were limited in number by the amount of die "periphery" available (bond pads are usually located along the edges of a die). In response to this, some ASIC manufacturers now offer various "high I/O" ASIC configurations. Among these are NEC Electronics of Mountain View, Calif., and Hitachi America of Brisbane, Calif.
In an article entitled "Emphasis shifts from density to I/O in low-density arrays", Computer Design, October 1991, this trend is described. As described therein, NEC Electronics' CMOS-6V gate arrays have circuit densities of from approximately 5,000 to 30,000 gates and I/O densities of from 140 to 220 I/O pads. This is accomplished by reducing the I/O pad pitch (providing smaller bond pads). Hitachi America provides a CMOS HC62G series which has circuit densities of from 14,000 to 35,000 gates and from 160 to 240 I/O pads by reducing I/O pad pitch and by staggering the I/O pads in two rows along the edges of the ASIC dies.
As microprocessor bus widths and computing parallelism increase, the need for even greater numbers of I/O pads on ASICs is becoming apparent.
Techniques for providing large numbers of I/O pads on a semiconductor die, relative to its circuit area are described in co-pending, commonly owned U.S. patent application Ser. No. 07/916,328 filed on Jul. 17, 1992 by Rostoker, incorporated herein by reference. This application describes "certain non-square" die shapes which have a greater ratio of die periphery to die area than rectangular dies.
Additional techniques for providing increased I/O pad density are described in co-pending commonly owned U.S. patent application Ser. No. 07/935,449 filed on Aug. 25, 1992 by Rostoker, incorporated herein by reference. This application describes "certain non-square" bond pads, which can be arranged with greater density than square bond pads.
Another technique for providing large numbers of I/O pads involves providing semiconductor dies with bond pads (electrical connection points) disposed on both surfaces of the die. Dies of this type are described in co-pending commonly owned U.S. patent application Ser. No. 07/975,185, filed on Nov. 12, 1992 by Rostoker, incorporated herein by reference.
While many techniques have been proposed for providing large numbers of I/O pads on semiconductor dies, particularly ASICs, semiconductor packaging has remained relatively unchanged. Typically, connection points (e.g., "pins" or leads) are disposed on the outer surface of the package for establishing electrical connections to a die contained within the package. The "pins" are connected to the die via conductive traces or lines which fan into the area in the immediate vicinity of the die. This area is referred to as the "die-receiving area" of the package. While packages are available with hundreds of pins, these are generally designed for large dies with relatively large I/O pad pitch, and provide a relatively large die-receiving area. It is often difficult to provide the required densely spaced conductive traces in a small die receiving area, since the conductive traces are extremely close together (low pitch), and often need to `fan-in` towards the die-receiving area.
Leadframe-type packages (e.g., TAB--Tape Automated Bonding) are particularly strained by fine (low) I/O pitch, since it is extremely difficult or impossible to provide a conductive leadframe with any kind of structural integrity when the leads become too small. When a large die size is used in conjunction with a leadframe-type package, the leads are spaced farther apart (and therefore may be larger) than when a small die size with the same number of I/O points is used. The most desirable and least expensive leadframes are "punched" out of a sheet of metal. High lead density, however, requires more expensive techniques (e.g. chemical etching) to produce leadframes.
Other approaches to high I/O density include multi-tier ceramic packages.